The present invention relates, in general, to electronics, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages.
According to the recent demand for miniaturization and high performance of electronic devices, a variety of processes for providing a high-performance semiconductor package are researched and developed. One of the processes for providing a high-performance semiconductor package is to increase a capacity of a memory chip, that is, to achieve high integration of memory chips. The high integration of memory chips can be achieved by packing as many cells as possible in a limited space of a semiconductor die.
However, the high integration of memory chips requires highly sophisticated techniques, including, for example, a need for attaining precise, fine linewidths, and a long time for development. Alternatively, a semiconductor die stacking technique has been proposed to provide a high-capacity semiconductor module. A technique of fabricating a package on a level of a wafer having a plurality of semiconductor dies formed thereon has also been proposed. In addition to requiring expensive and complex manufacturing techniques, each of these techniques lacks in circuit pattern redesign flexibility.
Accordingly, it is desirable to have a structure and a method of forming a packaged semiconductor device that addresses the issues noted previously as well as others. It is also desirable for the structure and method to be easily incorporated into manufacturing flows, and to be cost effective.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art, in one or more embodiments. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.